1. Field of the Invention
The present invention relates to interconnect structures for high-speed microprocessors, application specific integrated circuits (ASICs), and related high speed IC's. More particularly, the present invention provides low- or ultra low-dielectric constant (k) interconnect structures having enhanced circuit speed, precise values of conductor resistance, and improved mechanical integrity.
2. Description of the Prior Art
Many low-k dielectric plus Cu interconnect structures of the dual damascene type are known. For an example of the dual damascene process wherein SiLK™ has been used as a low-k dielectric material, reference is made to U.S. Pat. No. 6,383,920, assigned to the same assignee as the present invention, and is incorporated herein by reference in its entirety, as if fully set forth herein.
Integration with low and ultra-low dielectric constant (k) materials require a chemical mechanical planarization (CMP) polish stop layer in order to protect the underlying dielectric and prevent erosion and dishing of the low-k dielectric. Typically, chemical vapor deposition (CVD) materials with significantly higher dielectric constants (compared to the interlevel dielectric insulator materials) are applied directly to the line level dielectric materials forming a hardmask.
After CMP, a continuous layer of the CVD CMP polish stop layer must remain in the structure to prevent subsequent damage to the dielectric. In addition, the thickness must be sufficient that any non-uniformity in the CMP from center to edge or areas with varying metal fill will not lead to pin holes or areas where the CMP polish stop layer has been completely eroded. Therefore a higher dielectric constant material (typically SiC with k=4.1) must remain in the structure resulting in an increase in the effective dielectric constant.